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LVT22V10 3V high speed, universal PLD device
Product specification Supersedes data of 1996 Mar 12 IC13 Data Handbook 1998 Feb 10
Philips Semiconductors
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
FEATURES
* Fastest 3V PLD * Supports 3/5V mixed systems * Low ground bounce (<1.1V worst case) * Live insertion/extraction permitted * Bus-hold data inputs eliminate the need for external pull-up * Metastable hardened device * High output drive capability: 32mA/-16mA * Varied product term distribution with up to 16 product terms per * Programmable output polarity * Available in 300 mil-wide 24-pin Plastic Small Outline Package * Design support provided for third party CAD development and
programming hardware output for complex functions resistors to hold unused inputs
PIN CONFIGURATIONS
D and N Packages
I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 24 VCC 23 F9 22 F8 21 F7 20 F6 19 F5 18 F4 17 F3 16 F2 15 F1 14 F0 13 I11
I9 10 I10 11 GND 12
DESCRIPTION
The LVT22V10 is a versatile PAL(R) device fabricated on the Philips BiCMOS QUBiC process. The QUBiC process produces very high speed 3V devices (7.5ns) which have excellent noise characteristics. Ground bounce of an output held low while the remaining 9 outputs switch from high to low is typically less than 0.7V. VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V. The LVT22V10 was designed to support mixed 3/5V systems. The inputs are capable of handling 7V while the outputs can be pulled up to 7V. The designer can interface directly from 5V outputs (CMOS full rail or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V TTL input directly, or in the case of a CMOS input, the LVT output can interface with the use of an external pull-up resistor. Finally, no external pull-up resistors are needed on unused input pins due to a bus-hold data structure designed into the LVT input. The LVT22V10 has been designed with high drive outputs (32mA sink and 16mA source currents), which allows for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard PLDs. The LVT22V10 outputs are designed to support Live Insertion/Extraction into powered up systems. The output is specially designed so that during VCC ramp, the output remains 3-Stated until VCC [ 2.1V. At that time the outputs become fully functional depending upon device inputs. (See DC Electrical Characteristics, Symbol IPU/PD, Page 5). In addition when an LVT22V10 output is tied to a 5V bus, no bus current is loaded. The LVT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.
N = Plastic Dual In-Line Package (300mil-wide) D = Plastic Small Outline Large (300mil-wide) Package
A Package (standard)
I2 4 I3 5 I4 6 I5 7 NC 8 I6 9 GND 10 I8 11 12 I9 13 14 15 16 17 18 I1 3 CLK/ I0 NC VCC F9 F8 2 1 28 27 26 25 F7 24 F6 23 F5 22 NC 21 F4 20 F3 19 F2
I10 GND NC I11 F0 F1
A = Plastic Leaded Chip Carrier
A Package (evolutionary)
I2 4 I3 5 I4 6 I5 7 GND 8 I6 9 I7 10 I8 11 12 I9 13 14 15 16 17 18 I1 3 CLK/ I0 VCC VCC F9 F8 2 1 28 27 26 25 F7 24 F6 23 F5 22 GND 21 F4 20 F3 19 F2
I10 GND GND I11 F0 F1
A = Plastic Leaded Chip Carrier
SP00436
(R)PAL is a registered trademark of Advanced Micro Devices, Inc.
1998 Feb 10
2
853-1759 18947
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
ORDERING INFORMATION
PACKAGES 24-Pin Plastic DIP (300mil) 28-Pin PLCC (standard pinout) 28-Pin PLCC (evolutionary pinout) 24-Pin Plastic SOL ORDER CODE LVT22V10-7N (8.0ns device) DWG NUMBER SOT222-1 SOT261-3 SOT261-3 SOT137-1
LVT22V10B7A (7.5ns device) LVT22V10-7A LVT22V10-7D (7.5ns device) (8.0ns device)
PIN LABEL DESCRIPTIONS
SYMBOL I1 - I11 F0 - F9 CLK/I0 VCC GND NC DESCRIPTION Dedicated Input Macro Cell Input/Output Clock Input/Dedicated Input Supply Voltage Ground No Connection
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
OPERATING RANGES
RATINGS SYMBOL VCC Tamb PARAMETER MIN Supply voltage Operating free-air temperature +3.0 0 MAX +3.6 +75 VDC C UNIT
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VCC VIN VOUT IIN IOUT Tstg Supply voltage2 Input voltage2 Output voltage3 Input currents Output currents Storage temperature range -65 PARAMETER RATINGS MIN -0.5 -0.5 -0.5 -30 MAX +4.6 7 5.5 +30 +100 +150 UNIT VDC VDC VDC mA mA C
NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Except in programming mode. 3. Outputs can be pulled up to 7V via external pull-up resistor.
1998 Feb 10
3
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
TEST CIRCUIT AND WAVEFORMS
6.0V VCC OPEN RL GND 90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 10% 0V CL RL tTLH (tR) tTHL (tF) 90% VM tW 10% 0V AMP (V) tW 90% VM AMP (V)
VIN PULSE GENERATOR RT D.U.T.
VOUT
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH Open 6V GND
90% POSITIVE PULSE 10% VM
VM = 1.5V Input Pulse Definition
INPUT PULSE REQUIREMENTS FAMILY Amplitude LVT 3.0V Rep. Rate 10MHz tW 500ns tR 2.5ns tF 2.5ns
SP00385
1998 Feb 10
4
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
DC ELECTRICAL CHARACTERISTICS
Over operating ranges. SYMBOL Input voltage VIL VIH VI Low High Clamp VCC = MIN VCC = MAX VCC = MIN, IIN = -18mA VCC = MIN to MAX, VI = VIH or VIL VOH High-level output voltage VCC = MIN VI = VIH or VIL MIN, VCC = MIN to MAX, VI = VIH or VIL VOL Low-level output voltage VCC = MIN VI = VIH or VIL MIN, IOH = -100 A IOH = -16mA IOH = -5.5 mA IOL = 100A IOL = 32 mA IOL = 16 mA VCC-0.2 2.0 2.4 0.2 0.5 0.4 -10 10 10 20 75 -75 500 -500 10 100 100 2.0 -1.2 0.8 V V V V V V V V V A A A A A A A A A A A PARAMETER TEST CONDITIONS1 LIMITS MIN MAX UNIT
Output voltage
Input current IIL IIH II II IBHL IBHH IBHLO IBHHO IOFF IEX IPU/PD Low High Max input current Pin 1 (program) Bus hold low sustaining current2 Bus hold high sustaining current3 Bus hold low overdrive current4, 9 Bus hold high overdrive Output off current Current into an output in high state when VO > VCC Power-up/down 3-State output current8 Output leakage6 current5, 9 VCC = MAX, VIN = 0.0V VCC = MAX, VIN = VCC VCC = MAX, VIN = 5.5V VCC = MAX, VIN = 5.5V VCC = 3V, VI = 0.8V VCC = 3V, VI = 2V VCC = 3.6V VCC = 3.6V VCC = 0V, VI or VO = 0 to 4.5V VO = 5.5V, VCC = 3.0V VCC <1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = X VCC = MAX IOZH IOZL ISC ICC VIN = VIL or VIH, VOUT = 5.5V VIN = VIL or VIH, VOUT =0V VOUT = 0.5V VCC = 3.6V, Outputs enabled, VI = VCC or GND; IO = 0 MIN VCC = 3.0V, 25C, CL = 50pF (including jig capacitance) VCC = 3.3V, 25C, CL = 50pF , , (including jig capacitance) LVT22V10-7 LVT22V10B7 2.2 -30 10 -10 -220 170 TYP 2.3 0.7 1.0 1.1 1.1 MAX A A mA mA UNIT V V V Output leakage6 Short circuit7 VCC supply current
Output current
Ground/VCC Bounce VOHV VOLP Maximum dynamic VOH Maximum dynamic VOL
NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. The bus hold circuit can sink at least the minimum low sustaining current at VIL MAX. IBHL should be measured after lowering VIN to GND and then raising it to VIL MAX. 3. The bus hold circuit can source at least the minimum high sustaining current at VIH MIN. IBHL should be measured after raising VIN to VCC and then lowering it to VIH MIN. 4. An external driver must source at least IBHLO to switch this node from low to high. 5. An external driver must sink at least IBHHO to switch this node from high to low. 6. I/O pin leakage is the worst case of IOZX or IIX (where X = H or L). 7. No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 8. This parameter is valid for any VCC between 0V and 1.2 V with a transition time up to 10 mS. From VCC = 1.2 to VCC = 3.3V 0.3V a transition time of 100 S is permitted. X = Don't care. 9. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where input current may be affected. 1998 Feb 10 5
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
AC ELECTRICAL CHARACTERISTICS
Over commercial operating temperature range. SYMBOL PARAMETER Input or feedback to non-registered output2 g PLCC package tPD Input or feedback to non-registered output2 g DIP and SOL packages tS tH tCO tCF tAR tARW tARR tSPR tWL tWH Setup time from input, feedback or SP to Clock Hold time Clock to output Clock to feedback3 Asynchronous Reset to registered output Asynchronous Reset width Asynchronous Reset recovery time Synchronous Preset recovery time Width of Clock LOW Width of Clock HIGH Maximum frequency; External feedback 1/(tS + tCO)4 Maximum frequency; Internal feedback 1/(tS + tCF)4 Input to Output Enable5 Input to Output Disable5 5.0 5.0 5.0 3.0 3.0 95 118 8.5 8.5 TEST CONDITIONS1 MIN Active-LOW Active-HIGH Active-LOW Active-HIGH 5.5 0 5.0 3.0 12.0 LIMITS UNIT TYP MAX 7.5 7.5 8.0 8.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns
fMAX
tEA tER
Capacitance6 Input Capacitance (Pin 1) CIN COUT Input Capacitance (Others) Output Capacitance VIN = 2.0V VIN = 2.0V VOUT = 2.0V VCC = 3.3V, Tamb = 25C, f = 1MH 1MHz 6 6 8 pF pF pF
NOTES: 1. Test Conditions: R1 = 500, R2 =500 2. tPD is tested with switch S1 open and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V. 3. Calculated from measured fMAX internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.3V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.3V) level with S1 closed. 6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
1998 Feb 10
6
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
PRODUCT FEATURES Low Ground Bounce
The Philips Semiconductors BiCMOS QUBiC process results in exceptional noise immunity. Ground bounce is noise that is generated on a non-switching active low output when other outputs on the device switch from high to low. The worst case condition occurs when 9 outputs simultaneously switch from high to low and the tenth output is active low. The ground bounce on this tenth output for Philips LVT22V10 is typically less than 0.7V.
product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save "DeMorganizing" efforts. Selection is controlled by programmable bit S0 in the Output Macro Cell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be Active-HIGH (S0 = 1).
VCC Bounce
VCC bounce occurs on a non-switching active high output when other outputs are making a low to high transition. This specification is important to consider in 3.3V designs because of the reduced noise margin between VCC and VOH of only 1.3V relative to the traditional 5V system's noise margin of 3V. The Philips LVT22V10 VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V in magnitude.
Preset/Reset
For initialization, the LVT22V10 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW, independent of the clock. Note that Preset and Reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected.
Live Insertion/Extraction Capability
There are some inherent problems associated with inserting or extracting an unpowered module from a powered-up, active system. The LVT22V10 outputs have been designed such that any chance of bus contention, glitching or clamping is eliminated. Detailed information on this feature is provided in an application note AN051: Philips PLDs Support Live Insertion Applications.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the LVT22V10 will depend on the programmed output polarity. The VCC rise must be monotonic and the reset delay time is 1-10s maximum.
Bus Hold Input Structure
Bus Hold is a feature that maintains the input state of the device by incorporating a weak latch into the input structure. This latch maintains the input state until a minimum level of current (called the overdrive current) is supplied to change the input state. This is useful in bus applications where the bus is placed into a high impedance state. The LVT22V10's inputs, in this high impedance situation, maintain valid logic levels until the bus is actively driven to a new state.
Security Fuse
After programming and verification, LVT22V10 designs can be secured by programming the security fuse link. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is programmed.
Quality and Testability
The LVT22V10 offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies programmability and functionality of the device to provide the highest programming and post-programming functional yields.
Improved Fuse Verification Circuitry Increases Reliability
Philips has developed a new means of testing the integrity of fuses, both blown and intact fuses, which insures that all the fuses have been correctly programmed and that each and every fuse - whether "blown" or "intact" - is at the appropriate and optimal fuse resistance. This dual verify scheme represents a significant improvement over single reference voltage comparisons schemes that have been used for bipolar devices since the late 1980s. Detailed information on this feature is provided in an application note entitled Dual Verify Technique Increases Reliability of PLDs.
Technology
The BiCMOS LVT22V10 is fabricated with the Philips Semiconductors process known as QUBiC. QUBiC combines an advanced, state-of-the-art 1.0m (drawn feature size) CMOS process with an ultra fast bipolar process to achieve superior speed and drive capabilities. QUBiC incorporates three layers of Al/Cu interconnects for reduced chip size, and our proven Ti-W fuse technology ensures highest programming yields.
Programmable 3-stage Outputs
Each output has a 3-Stage output buffer with 3-State control. A product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be configured as a dedicated input if the buffer is always disabled.
Programming
The LVT22V10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABELTM CUPLTM and PALASM(R) 90 design software packages also support the LVT22V10 architecture. All packages allow Boolean and state equation entry formats, SNAP, ABEL and CUPL also accept, as input, schematic capture format.
Programmable Output Polarity
The polarity of each macro cell output can be Active-HIGH or Active-LOW, either to match output signal needs or to reduce
ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp.
1998 Feb 10
7
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
Output Register Preload
The register on the LVT22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The procedure for preloading follows: 1. Raise VCC to 3.3V 0.3V. 2. Set pin 2 or 3 to VHH to disable outputs and enable preload.
3. Apply the desired value (VILP/VIHP) to all registered output pins. Leave combinatorial output pins floating. 4. Clock Pin 1 from VILP to VIHP. 5. Remove VILP/VIHP from all registered output pins. 6. Lower pin 2 or 3 to VILP. 7. Enable the output registers according to the programmed pattern. 8. Verify VOL/VOH at all registered output pins. Note that the output pin signal will depend on the output polarity.
PRELOAD SET-UP
LIMITS SYMBOL VHH VILP VIHP tD tI/O Super-level input voltage Low-level input voltage High-level input voltage Delay time I/O valid after Pin 2 or 3 drops from VHH to VILP PARAMETER MIN 9.5 0 2.4 100 100 REC 9.5 0 3.3 200 MAX 10 0.8 3.6 1000 UNIT V V V ns ns
VHH PINS 2, 3 VILP
tD REGISTERED OUTPUTS tD CLOCK tD DATA IN tD
tD
tI/O VIHP VOH VOL VILP VIHP VILP
DATA OUT
SP00373
Output Register Preload Waveform
1998 Feb 10
8
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
LVT22V10 TIMING CHARACTERIZATION
Normalized tCO vs Temperature (VCC = 3.3V, output capacitance = 50pF, 5outputs switching)
1.05
Normalized tPD vs Temperature (VCC = 3.3V, output capacitance = 50pF, 5 outputs switching)
1.10
1.00 1.00
Normalized t CO
0.95
Normalized t PD
0.90 RISE FALL
0.90
RISE FALL 0.80 75 0 25 50 75
0.85 0 25 50
Temperature (C)
Temperature (C)
Normalized tCO vs VCC (temp = 25C, output capacitance = 50pF, 5 outputs switching)
1.20
Normalized tPD vs VCC (temp = 25C, output capacitance = 50pF, 5 outputs switching)
1.20
1.10
1.10
Normalized t CO
1.00
Normalized t PD
RISE FALL
1.00
0.90
0.90
RISE FALL 0.80
0.80 3.0 3.1 3.2 3.3 3.4 3.5 3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Supply Voltage (V)
Supply Voltage (V)
The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications.
SP00386
1998 Feb 10
9
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
LVT22V10 TIMING CHARACTERIZATION
Delta tCO vs Number of Outputs Switching (VCC = 3.3V, temp = 25C, output capacitance = 50pF)
100 0.10 0.00 0 -0.10 -100 -0.20 -0.30
Delta tPD vs Number of Outputs Switching (VCC = 3.3V, temp = 25C, output capacitance = 50pF)
Delta t CO (ps)
-200
(ns) Delta t PD
RISE FALL
-0.40 -0.50 -0.60 -0.70
-300
-400
-500
-0.80 -0.90
-600
RISE -1.00 -1.10 FALL
-700 1 2 3 4 5 6 7 8 9 10
1
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Number of Outputs Switching
Delta tCO vs Output Capacitance (VCC = 3.3V, temp = 25C, 5 Outputs Switching)
7.00 7.00
Delta tPD vs Output Capacitance (VCC = 3.3V, temp = 25C, 5 Outputs Switching)
6.00
6.00
5.00
5.00
(ns) Delta t PD
RISE FALL
Delta t CO (ns)
4.00
4.00
3.00
3.00
2.00
2.00
1.00
1.00
0.00
0.00
-1.00
-1.00
RISE FALL
-2.00 10 50 100 200 400
-2.00 10 50 100 200 400
Output Capacitance
Output Capacitance
The timing characterization represents the average values of a representative sample for each parameter. The data can be used to derate the MAX AC CHARACTERIZATION based upon the specific user design. Philips guarantees the MAX AC CHARACTERIZATION specifications.
SP00387
1998 Feb 10
10
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
LOGIC DIAGRAM
CLK/I0 1 0 0 1 9 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 AR
1 1 0 0 0 1 0 1
24
VCC
DAR SP
Q Q
23
F9
0 1
10
DAR Q Q 1 1 0 0 0 1 0 1
22
F8
20 I1 2 21
SP
0 1 1 1 0 0 0 1 0 1
DAR
33 I2 3 34
SP
Q Q
21
F7
0 1 1 1 0 0 0 1 0 1
DAR SP
Q Q
20
F6
48 I3 4 49
DAR SP Q Q 1 1 0 0 0 1 0 1 0 1
19
F5
65 I4 5 66
DAR SP Q Q
0 1 1 1 0 0 0 1 0 1
18
F4
82 I5 6 83
DAR SP Q Q
0 1 1 1 0 0 0 1 0 1
17
F3
97 I6 7 98
DAR Q Q
0 1 1 1 0 0 0 1 0 1
16
F2
110 I7 8 111
SP
0 1 1 1 0 0 0 1 0 1
DAR
121 9 122 130
SP
Q Q
15
F1
I8
0 1 1 1 0 0 0 1 0 1
DAR SP
Q Q
14
F0
I9
10 131 SP
0 1
I10 11 GND 12 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
13
I11
NOTE: Programmable connection.
SP00059
1998 Feb 10
11
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
FUNCTIONAL DIAGRAM
CLK/I0 1 11 I1 - I11
PROGRAMMABLE AND ARRAY (44 x 132)
8
10
12
14
16
16
14
12
10
8
RESET
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060A
Figure 1. Functional Diagram
FUNCTIONAL DESCRIPTION
The LVT22V10 allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Product terms with all fuses opened assume the logical HIGH state; product terms connected to both True and Complement of any single input assume the logical LOW state. The LVT22V10 has 12 inputs and 10 I/O Macro Cells (Figure 1). The Macro Cell allows one of four potential output configurations,
registered output or combinatorial I/O, Active-HIGH or Active-LOW (see Figure 2). The configuration choice is made according to the user's design specification and corresponding programming of the configuration bits S0 -S1. Multiplexer controls are connected to ground (0) through a programmable fuse link, selecting the "0" path through the multiplexer. Programming the fuse disconnects the control line from GND and it floats to VCC (1), selecting the "1" path.
1998 Feb 10
12
PRESET
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
OUTPUT MACRO CELL
S1
1 AR D CLK SP Q Q S1 S0 0 1 1 0 0 0 1 0 1 F 0 0 1 1
S0
0 1 0 1
OUTPUT CONFIGURATION
Registered/Active-LOW Registered/Active-HIGH Combinatorial/Active-LOW Combinatorial/Active-HIGH
0 = Unprogrammed fuse 1 = Programmed fuse
SP00375
Figure 2. Output Macro Cell Logic Diagram
AR D CLK SP Q Q
S0 = 0 S1 = 0 F
S0 = 0 S1 = 1 F
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
AR D CLK SP Q Q
S0 = 1 S1 = 0 F
S0 = 1 S1 = 1 F
b. Registered/Active-HIGH
d. Combinatorial/Active-HIGH
SP00376
Figure 3. Output Macro Cell Configurations
Registered Output Configuration
Each Macro Cell of the LVT22V10 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the registered configuration (S1 = 0), the array feedback is from Q of the flip-flop.
Variable Input/Output Pin Ratio
The LVT22V10 has twelve dedicated input lines, and each Macro Cell output can be an I/O pin. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity.
Combinatorial I/O Configuration
Any Macro Cell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin.
1998 Feb 10
13
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
INTERFACING IN MIXED 3V/5V SYSTEMS 3V Logic Driving 5V Logic
The LVT family has outputs that swing virtually between the power supply rails, thereby allowing direct interfacing with TTL switching levels. When interfacing the outputs of any of our 3V logic ICs with standard TTL-level logic inputs (bipolar or CMOS HCT), the output levels from the 3V logic are sufficient to directly drive the 5V logic. When driving CMOS-level devices (such as HC or AC), the output voltage from the 3V logic is insufficient to ensure reliable operation. This problem can be easily resolved by using a pull-up resistor at the interface.
metastable event occurs within the flop, the only outward manifestation of the event will be an increased clock-to-Q delay. This delay is a function of the metastability characteristics of the device, defined by and TO as described below. Since the outputs never glitch, oscillate, or remain in the linear region, the only metastable failure that can propagate further into the system is when the next flip-flop in the system samples the LVT22V10's output at precisely the same time it is making a logic transition. By allowing sufficient time for any increased clock-to-Q delay, propagation of metastable failures can be avoided. The following design example illustrates this concept.
Design Example
Suppose a designer wants to use the LVT22V10 for synchronizing asynchronous data that is arriving at 2MHz (as measured by a frequency counter), in a 3.3V system that has a clock frequency of 33MHz, at an ambient temperature of 25C. She has decided that she would like to sample the output of the LVT22V10 15ns after the clock edge to ensure that any clock-to-Q delays that were the result of the LVT22V10 internal metastability resolution circuitry have completed and the outputs have transitioned. The MTBF for this situation can be calculated by using the equation below: MTBF = e(t'/ )/TOFCF1 In this formula, FC is the frequency of the clock, F1 is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' > TCO). TO and are device parameters provided by the semiconductor manufacturer (refer to the following table for the LVT22V10 metastability specifications). TO and are derived from tests and can be most nearly be defined as follows: is a function of the rate at which a latch in a metastable state resolves that condition. TO is a function of the measurement of the propensity of a latch to enter a metastable state. TO is also a normalization constant, which is a very strong function of the normal propagation delay of the device. In this situation the F1 will be twice the data frequency, or 4MHz, because input events consist of both of low and high transitions. Thus, in this case, FC is 33MHz, F1 is 4MHz, is 317ps, t' is 15ns, and TO is 4.27 x 10-3 seconds. Using the above formula the actual MTBF for this situation is 1.26 x 109 seconds or 39 years for the LVT22V10.
5V Logic Driving 3V Logic
Since the LVT ICs do not have protection diodes between their inputs and VCC, the inputs of these devices can therefore withstand higher levels than the supply voltage, and they can be directly connected to 5V CMOS logic outputs. For the LVT family, the combination of low power dissipation with the live insertion feature, bus hold and full 5V input/output capability make this logic ideal for 3.3V backplane interfacing.
INTERFACING 3 VOLT AND 5 VOLT LOGIC
FROM 3V to 5V 5V to 3V LVT Output CMOS Rail Totem-Pole Open Drain TO TTL Inputs CMOS inputs LVT Input LVT Input LVT Input METHOD Direct Pull-up Direct Direct Pull-up
LVT22V10 METASTABLE HARDENED CHARACTERISTICS Metastable Hardened Characteristics
What is metastable hardened? Philips Semiconductors uses the term "metastable hardened" to describe a combination of two characteristic features. The first is a patented Philips circuit that prevents the outputs from glitching, oscillating, or remaining in the linear region under any circumstances, including setup and hold time violations. The second is the flip-flops' inherent ability of resolving the metastable condition. Philips provides complete data on the LVT22V10's metastable characteristics With the LVT22V10, any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a
Summary
The Philips LVT22V10 has on-chip circuitry that completely eliminates any output glitches, oscillations, or other output anomalies associated with metastable conditions. For outputs that are then used to generate clocks, control signals or other asynchronous data this represents an unparalleled level of reliability in a PLD. In addition, a complete set of metastability data is provided, that allows designers the ability to design robust systems where data is synchronously pipelined.
LVT22V10 VALUES FOR AND TO
VCC 3.0V 3.3V 3.6V 0C 829.00ps 358.00ps 237.00ps TO 1.16E-08 2.36E-04 2.66E-01 691.00ps 317.00ps 230.00ps 25C TO 1.09E-07 4.27E-03 6.47E-01 429.00ps 329.00ps 250.00ps 75C TO 2.27E-04 5.75E-03 1.13E+00
1998 Feb 10
14
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
SWITCHING WAVEFORMS
INPUT OR FEEDBACK VT tPD COMBINATORIAL OUTPUT VT CLOCK INPUT OR FEEDBACK VT tS tH VT tCO REGISTERED OUTPUT VT
Combinatorial Output
Registered Output
CLK
tS + tCF CLOCK VT LOGIC tS REGISTER
tCF
Clock to Feedback (fMAX Internal) (See Path at Right)
Clock to Feedback
INPUT tWH tER CLOCK VT OUTPUT tWL
VT tEA VOH - 0.3V VOL + 0.3V VT
Clock Width
Input to Output Disable/Enable
tARW INPUT ASSERTING ASYNCHRONOUS RESET VT tAR REGISTERED OUTPUT VT tARR CLOCK VT REGISTERED OUTPUT CLOCK INPUT ASSERTING SYNCHRONOUS PRESET VT tS tH VT tCO VT tSPR VT
Asynchronous Reset
Synchronous Preset
SP00388
NOTES: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 1.5ns max.
1998 Feb 10
15
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
"AND" ARRAY - (I, B)
I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B
P, D STATE INACTIVE1 CODE O STATE TRUE
P, D CODE H STATE COMPLEMENT
P, D CODE L STATE DON'T CARE
P, D CODE --
SP00008
NOTE: 1. This is the initial state.
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pattern. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation
of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
VCC POWER 2.7V
tPR REGISTERED ACTIVE-LOW OUTPUT tS CLOCK
tWL
Power-Up Reset Waveform
SP00389
LIMITS SYMBOL tPR tS tWL Power-up Reset Time Input or Feedback Setup Time Clock Width LOW PARAMETER MIN MAX 1 See AC Electrical Characteristics UNIT s
1998 Feb 10
16
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
1998 Feb 10
17
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
SOT261-3
1998 Feb 10
18
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1998 Feb 10
19
Philips Semiconductors
Product specification
3V high speed, universal PLD device
LVT22V10
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 02-98 Document order number: 9397 750 03313
Philips Semiconductors
1998 Feb 10 20

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